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Datasheet File OCR Text:

ST7263
LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
DATASHEET
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Up to 16Kbytes program memory Data RAM: up to 512 bytes with 64 bytes stack Run, Wait and Halt CPU modes 12 or 24 MHz oscillator RAM retention mode USB (Universal Serial Bus) Interface with DMA for low speed applications compliant with USB 1.5 Mbs specification (version 1.1) and USB HID specifications (version 1.0) Integrated 3.3V voltage regulator and transceivers Suspend and Resume operations 3 endpoints with programmable in/out configuration 19 programmable I/O lines with: - 8 high current I/Os (10mA at 1.3V) - 2 very high current pure Open Drain I/Os (25mA at 1.5V) - 8 lines individually programmable as interrupt inputs Optional Low Voltage Detector (LVD) Programmable Watchdog for system reliability 16-bit Timer with: - 2 Input Captures - 2 Output Compares - PWM Generation capabilities - External Clock input Asynchronous Serial Communications Interface (8K and 16K program memory versions only) I2C Multi Master Interface up to 400 KHz (16K program memory version only)
PSDIP32
CSDIP32W
SO34 (Shrink)
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8-bit A/D Converter (ADC) with 8 channels Fully static operation 63 basic instructions 17 main addressing modes 8x8 unsigned multiply instruction True bit manipulation Versatile Development Tools (under Windows) including assembler, linker, C-compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers
Table 1. Device Summary
Features ROM - OTP (bytes) RAM (stack) - bytes Peripherals Operating Supply CPU frequency Operating temperature Packages EPROM device ST72631 16K 512 (64) Watchdog, 16-bit timer, SCI, I2C, ADC, USB ST72632 8K 256 (64) Watchdog, 16-bit timer, SCI, ADC, USB 4.0V to 5.5V 8 Mhz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) 0C to +70C SO34/SDIP32 ST72E631 1 (CSDIP32W) Watchdog, 16-bit timer, ADC, USB ST72633 4K
Note 1: EPROM version for development only
August 2000
Rev. 1.8
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1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 EPROM/OTP PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 20 20
4.1.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 . ... 23 23 24 25 25 25 25 26 27 29 30 31 32 33 33 34 34 34 36
5.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
36 5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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5.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 IC BUS INTERFACE (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 48 48 48 49 54 54 54 54 56 60 60 61 65 65 65 65 66 71 73 73 73 73 75 78 78 79 84 84 84 85 85 85 86 87 87 88 88 88 88 88 89 89 90
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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7.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4 POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 98 7.7 CONTROL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.1 USB - Universal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.9 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 106 9.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 106 9.2 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST7263 Microcontrollers form a sub family of the ST7 dedicated to USB applications. The devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They operate at a 24MHz or 12 MHz oscillator frequency. Under software control, the ST7263 MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST7263 MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices include an ST7 Core, up to 16K program memory, up to 512 bytes RAM, 19 I/O lines and the following on-chip peripherals: - USB low speed interface with 3 endpoints with programmable in/out configuration using the DMA architecture with embedded 3.3V voltage regulator and transceivers (no external components are needed). - 8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs Figure 1. General Block Diagram
Internal CLOCK OSC/3 OSCILLATOR OSC/4 or OSC/2 (for USB) VDD VSS POWER SUPPLY WATCHDOG PORT B ADC PORT C SCI* (UART) USB SIE PC[2:0] (3 bits)
ADDRESS AND DATA BUS
- industry standard asynchronous SCI serial interface (not on all products - see device summary below) - digital Watchdog - 16-bit Timer featuring an External clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities - fast I2C Multi Master interface (not on all products - see device summary) - Low voltage (LVD) reset ensuring proper poweron or power-off of the device All ST7263 MCUs are available in ROM and OTP versions. The ST72E631 is the EPROM version of the ST7263 in CSDIP32 windowed packages. A specific mode is available to allow programming of the EPROM user memory array. This is set by a specific voltage source applied to the VPP/TEST pin.
OSCIN OSCOUT
I2C* PORT A 16-BIT TIMER PA[7:0] (8 bits)
RESET
CONTROL 8-BIT CORE ALU LVD USB DMA
PB[7:0] (8 bits)
VPP/TEST VDDA VSSA
PROGRAM MEMORY (4K/8K/16K Bytes) RAM (256/512 Bytes)
USBDP USBDM USBVCC
* not on all products (refer to Table 1: Device Summary)
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1.2 PIN DESCRIPTION Figure 2. 34-Pin SO Package Pinout
VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET NC AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) VPP/TEST AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1(10mA) * VPP on EPROM/OTP versions only
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
VDDA USBVCC USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA NC NC NC PA2(25mA)/SCL PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/OCMP1/IT3 PA7/OCMP2/IT4 PB0(10mA)/AIN0
Figure 3. 32-Pin SDIP Package Pinout
VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) VPP/TEST* AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1/(10mA)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDDA USBVCC USBDM USBDP VSSA PA0/MCO PA1(25mA)/SDA NC NC PA2(25mA)/SCL PA3/EXTCLK PA4/ICAP1/IT1 PA5/ICAP2/IT2 PA6/COMP1/IT3 PA7/COMP2/IT4 PB0(10mA)/AIN0
* VPP on EPROM/OTP versions only
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PIN DESCRIPTION (Cont'd) RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or VDD is low. It can be used to reset external peripherals. OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. VPP/TEST: EPROM programming input. This pin must be held low during normal operating modes. VDD/VSS (see Note 2): Main power supply and Ground voltages. VDDA/VSSA (see Note 2): Power Supply and Ground for analog peripherals. Table 2. Device Pin Description
Pin n Type SDIP32 SO34 Pin Name Level Output Input
Alternate Functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note 1: Adding two 100nF decoupling capacitors on Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performances. Note 2: To enhance reliability of operation, it is recommended to connect VDDA and VDD together on the application board. The same recommendations apply to VSSA and VSS.
Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function
1 2 3 4 5 6 7 8 -9
1 2 3 4 5 6 7 8 9
VDD OSCOUT OSCIN VSS PC2/USBOE PC1/TDO PC0/RDI RESET NC
S O I S I/O I/O I/O I/O -I/O CT 10mA X I/O CT 10mA X S I/O CT 10mA X I/O CT 10mA X I/O CT 10mA X I/O CT 10mA X I/O CT 10mA X I/O CT 10mA X I/O I/O CT CT X X X X X X X X X X X X X X X X X X X X X X X X X X CT CT CT X X X X X X X X
Power supply voltage (4V - 5.5V) Oscillator output Oscillator input Digital ground Port C2 Port C1 Port C0 Reset Not connected Port B7 Port B6 ADC analog input 7 ADC analog input 6 USB Output Enable SCI transmit data output *) SCI Receive Data Input *)
10 PB7/AIN7/IT8
10 11 PB6/AIN6/IT7 11 12 VPP/TEST 12 13 PB5/AIN5/IT6 13 14 PB4/AIN4/IT5 14 15 PB3/AIN3 15 16 PB2/AIN2 16 17 PB1/AIN1 17 18 PB0/AIN0 18 19 PA7/OCMP2/IT4 19 20 PA6/OCMP1/IT3
Supply for EPROM and test input Port B5 Port B4 Port B3 Port B2 Port B1 Port B0 Port A7 Port A6 ADC analog input 5 ADC analog input 4 ADC analog input 3 ADC analog input 2 ADC analog input 1 ADC Analog Input 0 Timer Output Compare 2 Timer Output Compare 1
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Pin n Type SDIP32 SO34 Pin Name
Level Output Input
Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Port A5 Port A4 Port A3 Port A2 Not connected Not connected Not connected T X X Port A1 Port A0 Analog ground USB bidirectional data (data +) USB bidirectional data (data -) USB power supply Analog supply voltage I2C serial data *) Main Clock Output Alternate Function
20 21 PA5/ICAP2/IT2 21 22 PA4/ICAP1/IT1 22 23 PA3/EXTCLK 23 24 PA2/SCL -- 25 NC 24 26 NC 25 27 NC 26 28 PA1/SDA 27 29 PA0/MCO 28 30 VSSA 29 31 USBDP 30 32 USBDM 31 33 USBVCC 32 34 VDDA
I/O I/O I/O
CT CT CT
X X X
X X
X X X T
Timer Input Capture 2 Timer Input Capture 1 Timer External Clock I2C serial clock *)
I/O CT 25mA X ---I/O CT 25mA X I/O S I/O I/O O S CT
*: if the peripheral is present on the device (see Table 1 Device Summary) Legend / Abbreviations for Figure 2 and Table 2: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: 10mA = 10mA high sink (on N-buffer only) 25mA = 25mA very high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, PP = push-pull, T = True open drain Refer to "I/O PORTS" on page 25 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state.
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1.3 EXTERNAL CONNECTIONS The following figure shows the recommended external connections for the device. The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode. The 10 nF and 0.1 F decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. Figure 4. Recommended External Connections The external reset network is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.
VPP VDD
10nF +
VDD
0.1F
VSS
Optional if Low Voltage Detector (LVD) is used
VDD
4.7K 0.1F
EXTERNAL RESET CIRCUIT 0.1F
RESET
See Clocks Section Or configure unused I/O ports by software as input with pull-up
OSCIN OSCOUT
VDD
10K
Unused I/O
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1.4 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 192 bytes of register location, up to 512 bytes of RAM and up to 16K bytes of user program memory. The RAM space includes up to 64 bytes for the stack from 0100h to 013Fh. Figure 5. Memory Map The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device
0000h 003Fh 0040h
HW Registers (see Table 4 256 Bytes RAM* 512 Bytes RAM*
0040h 00FFh 0100h
Short Addressing RAM (192 Bytes) Stack (64 Bytes)
023Fh 0240h
013Fh
Reserved
0040h BFFFh C000h 00FFh 0100h
Short Addressing RAM (192 Bytes) Stack (64 Bytes)
Program Memory* 16K Bytes
E000h
013Fh 0140h
8K Bytes
F000h
4K Bytes
FFEFh FFF0h
16-bit Addressing RAM (256 Bytes)
023Fh
FFFFh
Interrupt & Reset Vectors (see Table 3 on page 10)
* Program memory and RAM sizes are product dependent (see Table 1 Device Summary) Table 3. Interrupt Vector Map
Vector Address FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh FFFC-FFFDh FFFE-FFFFh Description USB Interrupt Vector SCI Interrupt Vector* I2C Interrupt Vector* TIMER Interrupt Vector IT1 to IT8 Interrupt Vector USB End Suspend Mode Interrupt Vector TRAP (software) Interrupt Vector RESET Vector Masked by I- bit I- bit I- bit I- bit I- bit I- bit none none Remarks Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt External Interrupts Internal Interrupt CPU Interrupt Exit from Halt Mode No No No No Yes Yes No Yes
* If the peripheral is present on the device (see Table 1 Device Summary)
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Table 4. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h SCI 1) TIM CR2 CR1 SR IC1HR IC1LR OC1HR OC1LR CHR CLR ACHR ACLR IC2HR IC2LR OC2HR OC2LR SR DR BRR CR1 CR2 ADC WDG ITIFRE MISCR DR CSR CR Block Register Label PADR PADDR PBDR PBDDR PCDR PCDDR Register name Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register Reserved (2 Bytes) Interrupt Register Miscellaneous Register ADC Data Register ADC control Status register Watchdog Control Register Reserved (4 Bytes) Timer Control Register 2 Timer Control Register 1 Timer Status Register Timer Input Capture High Register 1 Timer Input Capture Low Register 1 Timer Output Compare High Register 1 Timer Output Compare Low Register 1 Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture High Register 2 Timer Input Capture Low Register 2 Timer Output Compare High Register 2 Timer Output Compare Low Register 2 SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxxb xxh 00h R/W R/W Read only Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W Read only R/W R/W R/W R/W 00h F0h 00h 00h 7Fh R/W R/W Read only R/W R/W Reset Status 00h 00h 00h 00h 1111 x000b 1111 x000b Remarks R/W R/W R/W R/W R/W R/W
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Address 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
Block
Register Label PIDR DMAR IDR ISTR IMR CTLR
Register name USB PID Register USB DMA address Register USB Interrupt/DMA Register USB Interrupt Status Register USB Interrupt Mask Register USB Control Register USB Device Address Register USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B Reserved (7 Bytes)
Reset Status xxh xxh xxh 00h 00h xxxx 0110b 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb
Remarks Read only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
USB
DADDR EP0RA EP0RB EP1RA EP1RB EP2RA EP2RB
DR I2C1) OAR CCR SR2 SR1 CR
I2C Data Register Reserved I2C (7 Bits) Slave Address Register I2C Clock Control Register I C 2nd Status Register I2C 1st Status Register I2C Control Register
2
00h 00h 00h 00h 00h 00h
R/W R/W R/W Read only Read only R/W
Note 1. If the peripheral is present on the device (see Table 1 Device Summary)
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1.5 EPROM/OTP PROGRAM MEMORY The program memory of the ST72T63 may be programmed using the EPROM programming boards available from STMicroelectronics (see Table 26). 1.5.1 EPROM ERASURE ST72Exxx EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the ST72Exxx devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents. An Ultraviolet source of wave length 2537 A yielding a total integrated dosage of 15 Watt-sec/cm2 is required to erase the ST72Exxx. The device will be erased in 15 to 30 minutes if such a UV lamp with a 12mW/cm2 power rating is placed 1 inch from the device window without any interposed filters.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES
s s s s s s s s
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
2.3 CPU REGISTERS The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Figure 6. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable
Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
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CPU REGISTERS (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 3Fh
15 0 7
0 0 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (SP5 to SP0 bits are set) which is the stack higher address. Figure 7. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 013Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 013Fh Stack Lower Address = 0100h
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3 CLOCKS AND RESET
3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used). By setting the CLKDIV bit in the Miscellaneous Register, a 12 MHz external clock can be used giving an internal frequency of 4 MHz while maintaining a 6 MHz for USB (refer to Figure 10). The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 9 is recommended when using a crystal, and Table 5 Recommended Values for 24 MHz Crystal Resonator lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Figure 8. External Clock Source Connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 9. Crystal/Ceramic Resonator
OSCIN
RP
OSCOUT
COSCIN
COSCOUT
Table 5. Recommended Values for 24 MHz Crystal Resonator
RSMAX COSCIN COSCOUT 20 56pF 56pF 1-10 M 25 47pF 47pF 1-10 M 70 22pF 22pF 1-10 M
Figure 10. Clock block diagram
8 or 4 MHz CPU and peripherals)
RP
%3
CLKDIV 1 24 or 12 MHz Crystal 6 MHz (USB)
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification). 3.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 8. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of t OXOV (see Section 6.5 CONTROL TIMING).
%2 %2 %2
0
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3.2 RESET The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active. 3.2.1 Low Voltage Detector (LVD) Low voltage reset circuitry generates a reset when VDD is: s below VIT+ when VDD is rising, s below VIT- when VDD is falling. During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. The Low Voltage Detector can be disabled by setting the LVD bit of the Miscellaneous Register. 3.2.2 Watchdog Reset When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 11). 3.2.3 External Reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 14, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)
Section CPU clock running at 8 MHz Timer Prescaler reset to zero Timer Counter set to FFFCh All Timer enable bit set to 0 (disable) Data Direction Registers set to 0 (as Inputs) Set Stack Pointer to 013Fh Force Internal Address Bus to restart vector FFFEh,FFFFh Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable) Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable) Reset HALT latch Reset WAIT latch Disable Oscillator (for 4096 cycles) Set Timer Clock to 0 Watchdog counter reset Watchdog register reset Port data registers reset Other on-chip peripherals: registers reset X X X X X X X X X X X X X X X X X X X X RESET WAIT HALT
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Figure 11. Low Voltage Detector functional Diagram
RESET
Figure 12. Low Voltage Reset Signal Output
VIT+
VDD
LOW VOLTAGE DETECTOR
INTERNAL RESET
FROM WATCHDOG RESET
VIT-
VDD
RESET
Note: Hysteresis (VIT+-VIT-) = Vhys Figure 13. Temporization timing diagram after an internal Reset
VIT+
VDD
temporization (4096 CPU clock cycles)
Addresses
$FFFE
Figure 14. Reset Timing Diagram
tDDR VDD
OSCIN tOXOV fCPU
PC RESET
FFFE
FFFF
WATCHDOG RESET
4096 CPU CLOCK CYCLES DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys
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4 INTERRUPTS AND POWER SAVING MODES
4.1 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 7 Interrupt Mapping and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 15. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 7 Interrupt Mapping for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt can not be interrupted because the I bit is set by hardware entering in interrupt routine. In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 7 Interrupt Mapping). Non maskable software interrupts This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 15. Interrupts and Low power mode All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the "Exit from HALT" column in Table 7 Interrupt Mapping). External interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, pins ITl/PAn and ITm/ PBn (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset. Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both. - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - writing "0" to the corresponding bit in the status register or - an access to the status register while the flag is set followed by a read or write of an associated register. Notes: 1. The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed. 2. All interrupts allow the processor to leave the Wait low power mode. 3. Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset.
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INTERRUPTS (Cont'd) Figure 15. Interrupt Processing Flowchart
FROM RESET BIT I SET Y N N
INTERRUPT Y
FETCH NEXT INSTRUCTION
N
IRET Y STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 7. Interrupt Mapping
Source Block RESET TRAP USB 1 2 3 4 5 ITi TIMER I2C SCI USB Reset Software Interrupt End Suspend Mode External Interrupts Timer Peripheral Interrupts I2C Peripheral Interrupts SCI Peripheral Interrupts USB Peripheral Interrupts Register Label Priority Order Highest Priority Exit from HALT yes no yes Vector Address FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h no Lowest Priority FFF2h-FFF3h FFF0h-FFF1h
N
Description
N/A ISTR ITRFRE TIMSR I2CSR1 I2CSR2 SCISR ISTR
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INTERRUPTS (Cont'd) 4.1.1 Interrupt Register INTERRUPTS REGISTER (ITRFRE) Address: 0008h -- Read/Write Reset Value: 0000 0000 (00h)
7
IT8E IT7E IT6E IT5E IT4E IT3E IT2E
0
IT1E
Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits.
If an ITiE bit is set, the corresponding interrupt is generated when - a rising edge occurs on the pin PA4/IT1 or PA5/ IT2 or PB4/IT5 or PB5/IT6 or - a falling edge occurs on the pin PA6/IT3 or PA7/ IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. Note: Analog input must be disabled for interrupts coming from port B.
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4.2 POWER SAVING MODES 4.2.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f CPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. 4.2.2 HALT mode The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Figure 16. HALT Mode Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
OFF OFF OFF CLEARED
N RESET N
EXTERNAL INTERRUPT*
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET
4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 4.2.3 WAIT mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 17.
Figure 17. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEARED
N RESET N INTERRUPT
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON ON SET
IF RESET 4096 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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5 ON-CHIP PERIPHERALS
5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - analog signal input (ADC) - alternate signal input/output for the on-chip peripherals. - external interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 Functional description Each port is associated to 2 main registers: - Data Register (DR) - Data Direction Register (DDR) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 8. I/O Pin Functions
DDR 0 1 MODE Input Output
terrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, it masks the other ones. Output Mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note 1: All the inputs are triggered by a Schmitt trigger. Note 2: When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external In-
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I/O PORTS (Cont'd) Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 5.1.3 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC Input or true open drain.
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I/O PORTS (Cont'd) 5.1.4 Port A Table 9. Port A0, A3, A4, A5, A6, A7 Description
PORT A PA0 PA3 PA4 I/O Input* with pull-up with pull-up with pull-up Output push-pull push-pull Signal MCO (Main Clock Output) Timer EXTCLK Timer ICAP1 push-pull IT1 Schmitt triggered input Timer ICAP2 push-pull IT2 Schmitt triggered input Timer OCMP1 push-pull IT3 Schmitt triggered input Timer OCMP2 push-pull IT4 Schmitt triggered input IT2E = 1 (ITIFRE) OC1E = 1 IT3E = 1 (ITIFRE) OC2E = 1 IT4E = 1 (ITIFRE) IT1E = 1 (ITIFRE) Alternate Function Condition MCO = 1 (MISCR) CC1 =1 CC0 = 1 (Timer CR2)
PA5
with pull-up
PA6
with pull-up
PA7 *Reset State
with pull-up
Figure 18. PA0, PA3, PA4, PA5, PA6, PA7 Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE DDR LATCH DDR SEL
DATA BUS
VDD
PULL-UP
PAD
N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS
ALTERNATE INPUT
0
CMOS SCHMITT TRIGGER
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I/O PORTS (Cont'd)
Table 10. PA1, PA2 Description
PORT A PA1 PA2 *Reset State I/O Input* without pull-up without pull-up Output Very High Current open drain Very High Current open drain Alternate Function Signal SDA (I2C data) SCL (I2C clock) Condition I2C enable I2C enable
Figure 19. PA1, PA2 Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH
DDR LATCH
DATA BUS
PAD
DDR SEL
N-BUFFER
DR SEL
1 0
ALTERNATE ENABLE VSS CMOS SCHMITT TRIGGER
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I/O PORTS (Cont'd) 5.1.5 Port B Table 11. Port B Description
PORT B Input* PB0 PB1 PB2 PB3 PB4 without pull-up without pull-up without pull-up without pull-up without pull-up I/O Output push-pull push-pull push-pull push-pull push-pull IT5 Schmitt triggered input Analog input (ADC) PB5 without pull-up push-pull IT6 Schmitt triggered input Analog input (ADC) PB6 without pull-up push-pull IT7 Schmitt triggered input Analog input (ADC) PB7 *Reset State without pull-up push-pull IT8 Schmitt triggered input IT7E = 1 (ITIFRE) IT6E = 1 (ITIFRE) CH[2:0]= 111 (ADCCSR) IT5E = 1 (ITIFRE) CH[2:0]= 110 (ADCCSR) IT4E = 1 (ITIFRE) CH[2:0]= 101 (ADCCSR) Signal Analog input (ADC) Analog input (ADC) Analog input (ADC) Analog input (ADC) Analog input (ADC) Alternate Function Condition CH[2:0] = 000 (ADCCSR) CH[2:0] = 001 (ADCCSR) CH[2:0]= 010 (ADCCSR) CH[2:0]= 011 (ADCCSR) CH[2:0]= 100 (ADCCSR)
Figure 20. Port B Configuration
ALTERNATE ENABLE ALTERNATE OUTPUT DR LATCH ALTERNATE ENABLE DDR LATCH PAD ANALOG ENABLE (ADC) DDR SEL 1 0 P-BUFFER V DD
VDD
ALTERNATE INPUT
COMMON ANALOG RAIL
DATA BUS
ANALOG SWITCH N-BUFFER
DIODES
DR SEL
1 ALTERNATE ENABLE 0 DIGITAL ENABLE V SS
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I/O PORTS (Cont'd) 5.1.6 Port C Table 12. Port C Description
I/O PORT C Input* PC0 PC1 PC2 *Reset State with pull-up with pull-up with pull-up Output push-pull push-pull push-pull Signal RDI (SCI input) TDO (SCI output) USBOE (USB output enable) SCI enable USBOE =1 (MISCR) Condition Alternate Function
Figure 21. Port C Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE
DATA BUS
PULL-UP
VDD
DDR LATCH DDR SEL PAD
N-BUFFER
DR SEL
1
DIODES
ALTERNATE ENABLE
0 ALTERNATE INPUT
VSS
CMOS SCHMITT TRIGGER
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I/O PORTS (Cont'd) 5.1.7 Register Description DATA REGISTERS (PxDR) Port A Data Register (PADR): 0000h Port B Data Register (PBDR): 0002h Port C Data Register (PCDR): 0004h Read /Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 1111 x000 (FXh) Note: for Port C, unused bits (7-3) are not accessible.
7 D7 D6 D5 D4 D3 D2 D1 0
DATA DIRECTION REGISTER (PxDDR) Port A Data Direction Register (PADDR): 0001h Port B Data Direction Register (PBDDR): 0003h Port C Data Direction Register (PCDDR): 0005h Read/Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 1111 x000 (FXh) Note: for Port C, unused bits (7-3) are not accessible
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
D0
Bit 7:0 = D7-D0 Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
Table 13. I/O Ports Register Map
Address (Hex.) 00 01 02 03 04 05 Register Label PADR PADDR PBDR PBDDR PCDR PCDDR 7 MSB MSB MSB MSB MSB MSB 6 5 4 3 2 1 0 LSB LSB LSB LSB LSB LSB
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5.2 MISCELLANEOUS REGISTER Address: 0009h -- Read/Write Reset Value: 1111 0000 (F0h)
7
LVD CLKDIV USBOE
0
MCO
Bit 2 = CLKDIV Clock Divider. This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of a 12 MHz external oscillator (refer to Figure 10 on page 17). 0: 24 MHz external oscillator 1: 12 MHz external oscillator. Bit 1 = USBOE USB enable. If this bit is set, the port PC2 outputs the USB output enable signal (at "1" when the ST7 USB is transmitting data). Unused bits 7-4 are set. Bit 0 = MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port)
Bit 7:4 = Reserved Bit 3 = LVD Low Voltage Detector. This bit is set by software and only cleared by hardware after a reset. 0: LVD enabled 1: LVD disabled
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5.3 WATCHDOG TIMER (WDG) 5.3.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. Figure 22. Watchdog Block Diagram 5.3.2 Main Features s Programmable timer (64 increments of 49152 CPU cycles) s Programmable reset s Reset (if watchdog activated) when the T6 bit reaches zero
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /49152
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WATCHDOG TIMER (Cont'd) 5.3.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 14 . Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 14. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 393.216 6.144
reset immediately after waking up the microcontroller. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 5.3.4 Interrupts None. 5.3.5 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 5.3.3.1 Using Halt Mode with the WDG The HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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WATCHDOG TIMER (Cont'd) Table 15. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0C Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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5.4 16-BIT TIMER 5.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 5.4.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 5.4.3 Functional Description 5.4.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 23. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 5.4.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 24. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 25. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 26. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 5.4.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 1). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as a floating input).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 6). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 27. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 28. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 5.4.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1)
If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 8). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 9). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 29. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 30. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 31. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 5.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 1).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 10). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle
When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 32. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 33. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 5.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 1). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 11) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 5.4.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
5.4.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 5.4.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes 1) No Partially 2) Not Recommended 3) Not Recommended No No
See note 4 in Section 0.1.3.5 One Pulse Mode See note 5 in Section 0.1.3.5 One Pulse Mode 3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 5.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 16. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 17. 16-Bit Timer Register Map and Reset Values
Address (Hex.) 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Register Label CR2 Reset Value CR1 Reset Value SR Reset Value IC1HR Reset Value IC1LR Reset Value OC1HR Reset Value OC1LR Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value IC2HR Reset Value IC2LR Reset Value OC2HR Reset Value OC2LR Reset Value 7 OC1E 0 ICIE 0 ICF1 0 MSB MSB MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB MSB 1 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 6 OC2E 0 OCIE 0 OCF1 0 5 OPM 0 TOIE 0 TOF 0 4 PWM 0 FOLV2 0 ICF2 0 3 CC1 0 FOLV1 0 OCF2 0 2 CC0 0 OLVL2 0 0 0 1 IEDG2 0 IEDG1 0 0 0 0 EXEDG 0 OLVL1 0 0 0 LSB LSB LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB LSB 0 LSB 0
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5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 5.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 5.5.2 Main Features
s s s
5.5.3 General Description The interface is externally connected to another device by two pins (see Figure 1): - TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete.
s s
s
s s
s
s
Full duplex, asynchronous communications NRZ standard format (Mark/Space) Independently programmable transmit and receive baud rates up to 250K baud. Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags Two receiver wake-up modes: - Address bit (MSB) - Idle line Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Three error detection flags: - Overrun error - Noise error - Frame error Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 34. SCI Block Diagram
Write
Read
(Data Register) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 M
WAKE
-
-
-
TRANSMIT CONTROL CR2
TIE TCIE RIE ILIE TE
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
SR
RE RWU SBK TDRE TC RDRF IDLE OR NF FE -
SCI INTERRUPT CONTROL
TRANSMITTER CLOCK
fCPU
Transmitter Rate Control /2 /16 /PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receiver Rate Control
BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains 4 dedicated registers: - Two control registers (CR1 & CR2) - A status register (SR) - A baud rate register (BRR) Refer to the register descriptions in Section 0.1.7 for the definitions of each bit. 5.5.4.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register (see Figure 1). Figure 35. Word Length Programming The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
Next Data Frame
Next Stop Start Bit Bit Start Bit
Idle Frame
Break Frame
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit Start Bit Extra Start Bit '1'
Idle Frame Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR register. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. The following software sequence is always to clear the TDRE bit: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates that: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CC register. When a transmission is taking place, a write instruction to the DR register stores the data in the TDR register which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CC register. The following software sequence is always to clear the TC bit: 1. An access to the SR register 2. A write to the DR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2). As long as the SBK bit is set, the SCI sends break frames to the TDO pin. After clearing this bit by software, the SCI inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, i.e. before writing the next byte in the DR.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the DR register consists of a buffer (RDR) between the internal bus and the received shift register (see Figure 1). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR register. - Set the RE bit to enable the receiverto begin searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. When noise is detected in a frame: - The NF is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - The FE bit is set by hardware - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.4.4 Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (32*PR)*TR Rx = fCPU (32*PR)*RR should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the following two ways: - by Idle Line detection if the WAKE bit is reset, - by Address Mark detection if the WAKE bit is set. The Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. The Receiver wakes-up by Address Mark detection when it received a "1" as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
with: PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT0, SCT1 & SCT2 bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR0,SCR1 & SCR2 bits) All these bits are in the BRR register. Example: If fCPU is 8 MHz and if PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 bauds. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 5.5.4.5 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desirable that only the intended message recipient
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.5 Low Power Modes Mode WAIT HALT Description No effect on SCI. SCI interrupts exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
5.5.6 Interrupts
Interrupt Event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read Overrrun Error Detected Idle Line Detected Event Flag Enable Control Bit TDRE TIE TC TCIE RDRF RIE OR IDLE ILIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 5.5.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7
TDRE TC RDRF IDLE OR NF FE
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode. 0 0 Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set the RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Reserved, forced by hardware to 0.
Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift register as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 or by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when an Idle Line is detected. An interrupt is generated if ILIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 0: interrupt is inhibited CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in Read/Write the SR register Reset Value: Undefined 7
R8 T8 0 M WAKE 0 0
0
0
Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = Reserved, forced by hardware to 0. Bit 4 = M Word length. This bit determines the data length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark Bits 2:0 = Reserved, forced by hardware to 0. CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00 h) 7
TIE TCIE RIE ILIE TE RE RWU
Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SR register Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note: During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled, it resets the RDRF, IDLE, OR, NF and FE bits of the SR register. 1: Receiver is enabled and begins searching for a start bit. Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word.
0
SBK
Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR Dividing Factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh) 7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR Dividing Factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
0
SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling Factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Table 18. SCI Register Map and Reset Values
Address (Hex.) 20 21 22 23 24 Register Label SR Reset Value DR Reset Value BRR Reset Value CR1 Reset Value CR2 Reset Value 7 TDRE 1 DR7 x SCP1 0 R8 x TIE 0 6 TC 1 DR6 x SCP0 0 T8 x TCIE 0 5 RDRF 0 DR5 x SCT2 x 0 0 RIE 0 4 IDLE 0 DR4 x SCT1 x M x ILIE 0 3 OR 0 DR3 x SCT0 x WAKE x TE 0 2 NF 0 DR2 x SCR2 x 0 0 RE 0 1 FE 0 DR1 x SCR1 x 0 0 RWU 0 0 0 0 DR0 x SCR0 x 0 0 SBK 0
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5.6 USB INTERFACE (USB) 5.6.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out. 5.6.2 Main Features s USB Specification Version 1.1 Compliant s Supports Low-Speed USB Protocol s Two or Three Endpoints (including default one) depending on the device (see device feature list and register map) s CRC generation/checking, NRZI encoding/ decoding and bit-stuffing s USB Suspend/Resume operations s DMA Data transfers s On-Chip 3.3V Regulator s On-Chip USB Transceiver 5.6.3 Functional Description The block diagram in Figure 1, gives an overview of the USB interface hardware. Figure 36. USB Block Diagram 6 MHz For general information on the USB, refer to the "Universal Serial Bus Specifications" document available at http//:www.usb.org. Serial Interface Engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. DMA When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred.
ENDPOINT REGISTERS CPU
USBDM USBDP
Transceiver
SIE
DMA
Address, data buses and interrupts
USBVCC
3.3V Voltage Regulator
INTERRUPT REGISTERS MEMORY
USBGND
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USB INTERFACE (Cont'd) 5.6.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined
7
DA15 DA14 DA13 DA12 DA11 DA10 DA9
INTERRUPT/DMA REGISTER (IDR) Read / Write Reset Value: xxxx 0000 (x0h)
7 0
DA7 DA8 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0
0
Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure 2.
Bits 7:6 = DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure 2. Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2 When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet. Bits 3:0 = CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception. Note: Not valid for data transmission.
Figure 37. DMA Buffers
101111 Endpoint 2 TX 101000 100111 Endpoint 2 RX 100000 011111 011000 010111 010000 001111 001000 000111 Endpoint 0 RX DA15-6,000000 000000 Endpoint 1 TX Endpoint 1 RX Endpoint 0 TX
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USB INTERFACE (Cont'd) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h)
7 RX_ SEZ 0
INTERRUPT STATUS REGISTER (ISTR) Read / Write Reset Value: 0000 0000 (00h)
7
SUSP DOVR CTR ERR IOVR ESUSP RESET
0
SOF
TP3
TP2
0
0
0
RXD
0
Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. Note: PID bits 1 & 0 have a fixed value of 01. When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits as:
TP3 0 1 1 TP2 0 0 1 PID Name OUT IN SETUP
When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits cannot be set by software. Bit 7 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence. Bit 6 = DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can't answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected
Bits 5:3 Reserved. Forced by hardware to 0. Bit 2 = RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state Bit 1 = RXD Received data 0: No K-state 1: USB lines are in K-state This bit indicates the status of the RXD transceiver output (differential receiver output). Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wake-up due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1. Bit 0 = Reserved. Forced by hardware to 0.
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USB INTERFACE (Cont'd) Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected Bit 2 = ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a USB reset. Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND , XOR.. INTERRUPT MASK REGISTER (IMR) Read / Write Reset Value: 0000 0000 (00h)
7 SUS PM DOV RM CTR M ERR M IOVR M ESU SPM RES ETM 0 SOF M
of each bit, please refer to the corresponding bit description in ISTR. CONTROL REGISTER (CTLR) Read / Write Reset Value: 0000 0110 (06h)
7 0 0 0 0 RESUME PDWN FSUSP 0 FRES
Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay. Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 s for stabilisation of the power supply before using the USB interface. Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a "USB-RESET" interrupt will be generated if enabled.
Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation
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USB INTERFACE (Cont'd) DEVICE ADDRESS REGISTER (DADDR) Read / Write Reset Value: 0000 0000 (00h)
7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. Note: This register is also reset when a USB reset is received from the USB bus or forced through bit FRES in the CTLR register. ENDPOINT n REGISTER A (EPnRA) Read / Write Reset Value: 0000 xxxx (0xh)
7 ST_ OUT DTOG _TX STAT _TX1 STAT _TX0 TBC 3 TBC 2 TBC 1 0 TBC 0
Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software. Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed below:
STAT_TX1 STAT_TX0 Meaning DISABLED: transmission 0 0 transfers cannot be executed. STALL: the endpoint is stalled 0 1 and all transmission requests result in a STALL handshake. NAK: the endpoint is naked 1 0 and all transmission requests result in a NAK handshake. VALID: this endpoint is ena1 1 bled for transmission.
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and register map). Bit 7 = ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed.
These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 08).
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USB INTERFACE (Cont'd) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh)
7 DTOG _RX STAT _RX1 STAT _RX0 0
STAT_RX1 1
STAT_RX0 Meaning 0
1
CTRL EA3 EA2 EA1 EA0
1
NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception.
These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Bit 7 = CTRL Control. This bit should be 0. Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control Endpoint). Bit 6 = DTOG_RX Data toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet's data PID matches the receiver sequence bit. Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below:
STAT_RX1 0 STAT_RX0 Meaning 0
These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains "0001" and EP2RB contains "0010". ENDPOINT 0 REGISTER B (EP0RB) Read / Write Reset Value: 1000 0000 (80h)
7 DTOG RX STAT RX1 STAT RX0 0
1
0
0
0
0
This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset. Bit 7 = Forced by hardware to 1. Bits 6:4 = Refer to the EPnRB register for a description of these bits. Bits 3:0 = Forced by hardware to 0.
0
1
DISABLED: reception transfers cannot be executed. STALL: the endpoint is stalled and all reception requests result in a STALL handshake.
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USB INTERFACE (Cont'd) 5.6.5 Programming Considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (ISTR) bits. 5.6.5.1 Initializing the Registers At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests. 1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers. 2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization. 3. When addresses are received through this channel, update the content of the DADDR. 4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register. 5.6.5.2 Initializing DMA buffers The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 2. Each buffer is filled starting from the bottom (last 3 address bits=000) up. 5.6.5.3 Endpoint Initialization To be ready to receive: Set STAT_RX to VALID (11b) in EP0RB to enable reception. To be ready to transmit: 1. Write the data in the DMA transmit buffer. 2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field 3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA. Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly.
When the operation is completed, they can be accessed again to enable a new operation. 5.6.5.4 Interrupt Handling Start of Frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB Reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. End Suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates HALT mode. Correct Transfer (CTR) 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. 2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. Note: When a CTR interrupt occurs, the TP3TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register.
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USB INTERFACE (Cont'd) Table 19. USB Register Map and Reset Values
Address (Hex.) 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 Register Name PIDR Reset Value DMAR Reset Value IDR Reset Value ISTR Reset Value IMR Reset Value CTLR Reset Value DADDR Reset Value EP0RA Reset Value EP0RB Reset Value EP1RA Reset Value EP1RB Reset Value EP2RA Reset Value EP2RB Reset Value 7 TP3 x DA15 x DA7 x SUSP 0 SUSPM 0 0 0 0 0 ST_OUT 0 1 1 ST_OUT 0 CTRL 0 ST_OUT 0 CTRL 0 6 TP2 x DA14 x DA6 x DOVR 0 DOVRM 0 0 0 ADD6 0 5 0 0 DA13 x EP1 x CTR 0 CTRM 0 0 0 ADD5 4 0 0 DA12 x EP0 x ERR 0 ERRM 0 0 0 ADD4 3 0 0 DA11 x CNT3 0 IOVR 0 IOVRM 0 RESUME 0 ADD3 0 TBC3 x 0 0 TBC3 x EA3 x TBC3 x EA3 x 2 RX_SEZ 0 DA10 x CNT2 0 ESUSP 1 RXD 0 DA9 x CNT1 0 RESET 0 0 0 DA8 x CNT0 0 SOF 0 SOFM 0 FRES 0 ADD0 0 TBC0 x 0 0 TBC0 x EA0 x TBC0 x EA0 x
0 0 ESUSPM RESETM 0 PDWN 1 ADD2 0 TBC2 x 0 0 TBC2 x EA2 x TBC2 x EA2 x 0 FSUSP 1 ADD1 0 TBC1 x 0 0 TBC1 x EA1 x TBC1 x EA1 x
0 0 STAT_TX1 STAT_TX0 DTOG_TX 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 0 0 0 DTOG_TX STAT_TX1 STAT_TX0 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 0 0 0 DTOG_TX STAT_TX1 STAT_TX0 0 0 0 DTOG_RX STAT_RX1 STAT_RX0 0 0 0
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5.7 IC BUS INTERFACE (IC) 5.7.1 Introduction The IC Bus Interface serves as an interface between the microcontroller and the serial IC bus. It provides both multimaster and slave functions, and controls all IC bus-specific sequencing, protocol, arbitration and timing. It supports fast IC mode (400 kHz). 5.7.2 Main Features s Parallel-bus/IC protocol converter s Multi-master capability s 7-bit Addressing s Transmitter/Receiver flag s End-of-byte transmission flag s Transfer problem detection IC Master Features: s Clock generation s IC bus busy flag s Arbitration Lost Flag s End of byte transmission flag s Transmitter/Receiver Flag s Start bit detection flag s Start and Stop generation IC Slave Features: s Stop bit detection s IC bus busy flag s Detection of misplaced start or stop condition s Programmable IC Address detection s Transfer problem detection s End-of-byte transmission flag s Transmitter/Receiver flag 5.7.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled Figure 38. IC BUS Protocol SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION
VR02119B
handshake. The interrupts are enabled or disabled by software. The interface is connected to the IC bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard IC bus and a Fast IC bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: - Slave transmitter/receiver - Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, this allows Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition is the address byte; it is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 1.
ACK
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IC BUS INTERFACE (Cont'd) The Acknowledge function may be enabled and disabled by software. The IC interface address and/or general call address can be selected by software. The speed of the IC interface may be selected between Standard (0-100 kHz) and Fast IC (100400 kHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. Figure 39. IC Interface Block Diagram
The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on the IC bus mode. When the IC cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistor used depends on the application. When the IC cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
DATA REGISTER (DR)
SDAI SDA DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
SCLI SCL CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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IC BUS INTERFACE (Cont'd) 5.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 0.1.7. for the bit definitions. By default the IC interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. 5.7.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: - An Acknowledge pulse is generated if the ACK bit is set. - EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 3 Transfer sequencing EV1). Next, software must read the DR register to determine from the least significant bit if the slave must enter Receiver or Transmitter mode. Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - An Acknowledge pulse is generated if the ACK bit is set - EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 3 Transfer sequencing EV2). Slave Transmitter Following the address reception and after the SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 3 Transfer sequencing EV3). When the acknowledge pulse is received: - The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing Slave Communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: - EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 3 Transfer sequencing EV4). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop condition, then the interface discards the data, released the lines and waits for another Start condition. If it is a Start condition, then the interface discards the data and waits for the next slave address on the bus. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. Note: In both cases, the SCL line is not held low; however, the SDA line can remain low due to possible "0" bits transmitted last. It is then necessary to release both lines by software. How to Release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte.
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IC BUS INTERFACE (Cont'd) 5.7.4.2 Master Mode To switch from default Slave mode to Master mode, a Start condition generation is needed. Start Condition and Transmit Slave Address Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address byte, holding the SCL line low (see Figure 3 Transfer sequencing EV5). Then the slave address byte is sent to the SDA line via the internal shift register. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 3 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Master Receiver Following the address transmission and after the SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - An Acknowledge pulse is generated if if the ACK bit is set - EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 3 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface returns automatically to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 3 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if the ITE bit is set. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. - ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible "0" bits transmitted last. It is then necessary to release both lines by software.
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IC BUS INTERFACE (Cont'd) Figure 40. Transfer Sequencing Slave Receiver
S Address A EV1 Data1 A EV2 Data2 A EV2 ..... DataN A EV2 P EV4
Slave Transmitter
S Address A EV1 EV3 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3-1 P EV4
Master Receiver
S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN NA EV7 P
Master Transmitter
S EV5 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P
Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading the SR1 register. EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading the SR2 register. EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register. EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register. EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
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IC BUS INTERFACE (Cont'd) 5.7.5 Low Power Modes Mode WAIT Description No effect on IC interface. IC interrupts exit from Wait mode. IC registers are frozen. In Halt mode, the IC interface is inactive and does not acknowledge data on the bus. The IC interface resumes operation when the MCU is woken up by an interrupt with "exit from Halt mode" capability.
HALT
5.7.6 Interrupts Figure 41. Event Flags and Interrupt Generation
BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT
EVF
* * EVF can also be set by EV6 or an error from the SR2 register.
Interrupt Event End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event
Event Flag BTF ADSEL SB AF STOPF ARLO BERR
Enable Control Bit
ITE
Exit from Wait Yes Yes Yes Yes Yes Yes Yes
Exit from Halt No No No No No No No
The IC interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
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IC BUS INTERFACE (Cont'd) 5.7.7 Register Description IC CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 PE ENGC START ACK STOP 0 ITE
Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). - In Master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. - In Slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 4 for the relationship between the events and the interrupt. SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See Figure 3) is detected.
Bits 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: - When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the IC interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). - In master mode: 0: No start generation 1: Repeated start generation - In slave mode: 0: No start generation 1: Start generation when the bus is free
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IC BUS INTERFACE (Cont'd) IC STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)
7 EVF 0 TRA BUSY BTF ADSL M/SL 0 SB
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 3. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - ADSL=1 (Address matched in Slave mode while ACK=1) - SB=1 (Start condition generated in Master mode) - AF=1 (No acknowledge received after byte transmission) - STOPF=1 (Stop condition detected in Slave mode) - ARLO=1 (Arbitration lost in Master mode) - BERR=1 (Bus error, misplaced Start or Stop condition detected) - Address byte successfully transmitted in Master mode. Bit 6 = Reserved. Forced to 0 by hardware. Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 3). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated
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IC BUS INTERFACE (Cont'd) IC STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h)
7 0 0 0 AF 0 STOPF ARLO BERR GCAL
Bits 7:5 = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus
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IC BUS INTERFACE (Cont'd) IC CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)
7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 CC0
IC OWN ADDRESS REGISTER (OAR) Read / Write Reset Value: 0000 0000 (00h)
7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
Bit 7 = FM/SM Fast/Standard IC mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard IC mode 1: Fast IC mode Bits 6:0 = CC6-CC0 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the IC mode. They are not cleared when the interface is disabled (PE=0). - Standard mode (FM/SM=0): FSCL <= 100kHz FSCL = fCPU/(2x([CC6..CC0]+2)) - Fast mode (FM/SM=1): FSCL > 100kHz FSCL = fCPU/(3x([CC6..CC0]+2)) Note: The programmed FSCL assumes no load on SCL and SDA lines.
Bits 7:1 = ADD7-ADD1 Interface address. These bits define the IC bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don't care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored.
IC DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bits 7:0 = D7-D0 8-bit Data Register. These bits contains the byte to be received or transmitted on the bus. - Transmitter mode: Byte transmission start automatically when the software writes in the DR register. - Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the next data bytes are received one by one after reading the DR register.
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Table 20. I2C Register Map
Address (Hex.) 39 3B 3C 3D 3E 3F Register Name DR OAR CCR SR2 SR1 CR 7 6 5 4 3 2 1 0
FM/SM EVF TRA PE
DR7 .. DR0 ADD7 .. ADD0 CC6 .. CC0 AF STOPF BUSY BTF ENGC START
ARLO ADSL ACK
BERR M/SL STOP
GCAL SB ITE
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5.8 8-BIT A/D CONVERTER (ADC) 5.8.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 5.8.2 Main Features s 8-bit conversion s Up to 8 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/Off bit (to reduce consumption) The block diagram is shown in Figure 42.
Figure 42. ADC Block Diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
ANALOG MUX
SAMPLE & HOLD
ANALOG TO DIGITAL CONVERTER
fCPU
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(Data Register) DR
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8-BIT A/D CONVERTER (ADC) (Cont'd) 5.8.3 Functional Description The high level reference voltage VDDA must be connected externally to the V DD pin. The low level reference voltage V SSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Figure 43. Recommended Ext. Connections
VDD
0.1F
VDDA VSSA
ST7
RAIN VAIN Px.x/AINx
Characteristics: The conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. If input voltage is greater than or equal to VDD (voltage reference high) then results = FFh (full scale) without overflow indication. If input voltage VSS (voltage reference low) then the results = 00h. The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. The A/D converter is linear and the digital result of the conversion is given by the formula: Digital result = 255 x Input Voltage Reference Voltage
The accuracy of the conversion is described in the Electrical Characteristics Section. Procedure: Refer to the CSR and DR register description section for the bit definitions. Each analog input pin must be configured as input, no pull-up, no interrupt. Refer to the "I/O Ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 21 Channel Selection. - Set the ADON bit. Then the A/D converter is enabled after a stabilization time (typically 30 s). It then performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register. A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new conversion. 5.8.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
HALT
5.8.5 Interrupts None.
Where Reference Voltage is VDD - VSS.
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8-BIT A/D CONVERTER (ADC) (Cont'd) 5.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h)
7 COCO ADON 0 CH2 CH1 0 CH0
Table 21. Channel Selection Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. Bit 5 = ADON A/D converter On This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. Note: A typical 30 s delay time is necessary for the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. Bits 2:0: CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
*IMPORTANT NOTE: The number of pins AND the channel selection vary according to the device. REFER TO THE DEVICE PINOUT).
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 AD0
Bit 7:0 = AD[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Reading this register resets the COCO flag.
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6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 22. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (Bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+127 00..FF 00..FF 00..FF 00..FF byte 00..FF byte
1)
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 00..FF 00..FF 00..FF 00..FF 00..FF byte word byte word byte +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
PC-128/PC+1271)
btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
6.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 6.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 6.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
6.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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ST7 ADDRESSING MODES (Cont'd) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 23. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
SWAP CALL, JP
Swap Nibbles Call or Jump subroutine
6.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC Clear
Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations
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6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS Devices of the ST72 family contain circuitry to protect the inputs against damage due to high static voltage or electric fields. Nevertheless, it is recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to voltages above those quoted in the Absolute Maximum Ratings. For proper operation, it is recommended that the input voltage V IN be constrained within the range: (VSS - 0.3V) VIN (VDD + 0.3V) To enhance reliability of operation, it is recommended to configure unused I/Os as inputs and to connect them to an appropriate logic voltage level such as VSS or VDD. it is also recommended to connect VDDA and VDD together on application. (same remark for VSSA and VSS). All the voltage in the following tables are referenced to VSS. Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 24. Absolute Maximum Ratings (Voltage Referenced to VSS )
Symbol VDD VDDA |VDDA - VDD| |VSSA - VSS| IVDD - IVSS VIN VOUT TA TSTG TJ PD ESD Ratings Recommended Supply Voltage Analog Reference Voltage Max. variations on Power Line Max. variations on Ground Line Total current into VDD/VSS Input Voltage Output Voltage Ambient Temperature Range Storage Temperature Range Junction Temperature Power Dissipation ESD susceptibility Value - 0.3 to +6.0 - 0.3 to +6.0 50 50 80/80 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 TL to TH 0 to + 70 -65 to +150 150 350 2000 Unit V V mV mV mA V V C C C mW V
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7.2 THERMAL CHARACTERISTICS The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1)* Therefore: Where: - TA is the Ambient Temperature in C, - JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, - P D is the sum of PINT and P I/O, - P INT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power - P I/O represents the Power Dissipation on Input and Output Pins; User Determined. For most applications P I/O Symbol JA Package SO34 PSDIP32 Typical Value 70 50 Unit C/W
An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K/ (TJ + 273C) (2)
K = PD x (TA + 273C) + JA x P D2 (3) Where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known T A. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.
(*): Maximum chip dissipation can directly be obtained from Tj (max), JA and TA parameters.
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7.3 OPERATING CONDITIONS General Operating Conditions (TA = 0 to +70C unless otherwise specified)
Symbol Parameter Conditions fCPU = 4 MHz ; USB not guaranteed fCPU = 8 MHz ; USB not guaranteed VDD Supply voltage
1)
Min 3.00 VIT+ 4.0 5.25 12
Max 4.00 4.00 5.25 5.50 24
Unit V
fCPU = 8 MHz or 4 MHz USB guaranteed fCPU = 8 MHz or 4 MHz USB not guaranteed
V
fOSC
External clock frequency
MHz
Note 1: USB 1.1 specifies that the power supply must be between 4.00 and 5.25 Volts. The USB cell is therefore guaranteed only in that range.
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7.4 POWER CONSUMPTION (TA = 0 to +70C unless otherwise specified)
GENERAL Symbol VDD VDDA Parameter Operating Supply Voltage Analog Reference Voltage CPU RUN mode (see Note 1) IDD CPU WAIT mode (See Note 2) CPU HALT mode (see Note 3) USB Suspend mode (see Note 4) Note 1: Note 2: Note 3: Note 4: All peripherals running. Oscillator, 16-bit Timer (free running counter) and watchdog running. All others peripherals (including EPROM/RAM memories) disabled. CPU in HALT mode, USB Transceiver disabled, Low Voltage Reset function enabled. Low voltage reset function enabled. CPU in HALT mode. USB in suspend mode. External pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to VSSA) connected on drivers. VDD = 5.5 V except in USB Suspend mode where VDD = 5.25 V I/O in input mode fCPU = 8 MHz, TA = 20C (For VDD : see Note 5) 350 Conditions RUN & WAIT mode fOSC = 24 MHz fCPU = 8 MHz 4 5 14 8 5.5 20 12 100 450 V mA mA A A 4 5 5.5 V Min Typ. Max Unit
Note 5:
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7.5 I/O PORT CHARACTERISTICS (TA = 0 to +70C unless otherwise specified)
STANDARD I/O PORT PINS Symbol Parameter Output Low Level Voltage Port A1, Port A2 (High Current open drain) VOL Output Low Level Voltage Port A0, Port A(3:7), Port C(0:2), Push Pull Output Low Level Voltage Port B (0:7), Push Pull VOH VOH VIH VIL RPU CIO tf(IO)out tr(IO)out tr(IO)out Output High Level Voltage Port A0, Port A(3:7), Port C(0:2) Push Pull Output High Level Voltage Port B (0:7) Push Pull Input High Level Voltage PA(0:7),PB(0:7),PC(0:2),RESET Input Low Voltage PA(0-7), PB(0-7), PC(0-2), RESET Pull-up resistor I/O Pin Capacitance 1) Output High to Low Level Fall Time All I/O ports Output Low to High Level Rise Time I/O ports in Push Pull mode External Interrupt pulse time 1) Conditions IOL = -25mA VDD=5V IOL = -1.6mA VDD=5V IOL = -10mA VDD=5V IOH = 1.6mA IOH = 10mA Leading Edge Trailing Edge VDD = 5V Min VDD-0.8 VDD-1.3 0.7xVDD VSS 80 100 5 CL=50pF Between 10% and 90% 1 25 2) 25 2) Typ Max 1.5 0.4 1.3 VDD 0.3xVDD 120 Unit V V V V V V V k pF ns ns tCPU
All voltages are referred to VSS unless otherwise specified. Note 1: Guaranteed by design, not tested in production. Note 2: Data based on characterization results, not tested in production.
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7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS
LOW VOLTAGE RESET Electrical Specifications Symbol VIT+ VITVhys Parameter Low Voltage Reset Threshold VDD rising Low Voltage Reset Threshold VDD falling Hysteresis (VIT+ - VIT-) Conditions VDD Max. Variation 50mV/s VDD Max. Variation 50mV/s Min 3.6 3.2 200 Typ 3.75 3.5 250 Max 4.0 3.7 Unit V V mV
7.7 CONTROL TIMING CHARACTERISTICS (Operating conditions TA = 0 to +70C unless otherwise specified)
CONTROL TIMINGS Symbol fOSC fCPU tRL tPORL TDOGL tDOG tOXOV tDDR Parameter Oscillator Frequency Operating Frequency External RESET Input pulse Width Internal Power Reset Duration Watchdog & Low Voltage Reset Output Pulse Width Watchdog Time-out Crystal Oscillator Start-up Time Power up rise time from VDD = 0 to 4V fcpu = 8MHz 1.5 4096 200 49152 6 3145728 384 50 100 Conditions Value Min Typ. Max 24 8 Unit MHz MHz tCPU tCPU ns tCPU ms ms ms
Note 1: The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles.
C
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7.8 COMMUNICATION INTERFACE CHARACTERISTICS The values given in the specifications of dedicated functions are generally not applicable for chips. Therefore, only the limits listed below are valid for the product. T = 0... +70C, VDD - VSS = 5 V unless otherwise specified. 7.8.1 USB - Universal Bus Interface (Operating conditions TA = 0 to +70C, VDD = 4.0 to 5.25V unless otherwise specified)
USB DC Electrical Characteristics Parameter Input Levels: Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High USBVCC: voltage level VOL VOH USBV RL of 1.5K ohms to 3.6v RL of 15K ohm to VSS VDD=5v 2.8 3.00 0.3 3.6 3.60 V V V VDI VCM VSE I(D+, D-) Includes VDI range 0.2 0.8 0.8 2.5 2.0 V V V Symbol Conditions Min. Max. Unit
Note 1: RL is the load connected on the USB drivers. Note 2: All the voltages are measured from the local ground potential.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 44. USB: Data signal Rise and fall time
Differential Data Lines
VCRS
Crossover points
VSS tf tr
USB: Low speed electrical characteristics Parameter Driver characteristics: Rise time Fall Time Rise/ Fall Time matching Output signal Crossover Voltage tr tf trfm VCRS Note 1,CL=50 pF Note 1, CL=600 pF Note 1, CL=50 pF Note 1, CL=600 pF tr/tf 80 1.3 75 300 120 2.0 75 300 ns ns ns ns % V Symbol Conditions Min Max Unit
Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 7.8.2 I 2C - Inter IC Control Interface
I2C/DDC-Bus Timings Parameter Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated Standard I2C Min 4.7 4.0 Max 1.3 0.6 Fast I2C Min Max Symbol TBUF THD:STA Unit ms
s s s s
ns ns ns ns ns pF
LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time
Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line
4.7 4.0 4.7 0 (1)
250 1000 300 4.0 400
1.3 0.6 0.6 0 (1)
100 20+0.1Cb 20+0.1Cb 0.6 400 300 300
TLOW THIGH TSU:STA 0.9(2) THD:DAT
TSU:DAT TR TF TSU:STO Cb
1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal Cb = total capacitance of one bus line in pF
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7.9 8-BIT ADC CHARACTERISTICS
Digital Result ADCDR 255 254 253 1LSB i deal V -V DDA SSA = ---------------------------------------256 (2) 7 6 5 4 3 2 1 0 1 V SA S 2 3 4 1 LS B(ideal) O E ILE D LE TU E (3) (1)
G E (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
TUE=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE=Offset Error: deviation between the first actual transition and the first ideal one. GE=Gain Error: deviation between the last ideal transition and the last actual one. DLE=Differential Linearity Error: maximum deviation between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin (LSBideal) 5 6 7 253 254 255 256 V DDA
ADC Analog to Digital Converter (8-bit) Symbol |TUE| OE GE |DLE| |ILE| VAIN IADC tSTAB tLOAD tCONV RAIN RADC Parameter Total unadjusted error* Offset error* Gain Error* Differential linearity error* Integral linearity error* Conversion range voltage A/D conversion supply current Stabilization time after enable ADC Sample capacitor loading time Hold conversion time External input resistor Internal input resistor fADC=fCPU=4MHz VDD=VDDA=5V 8 32 8 32 20 18 22 VSSA 1 30 fADC=fCPU=4MHz VDD=VDDA=5V -1 -2 Conditions Min Typ Max 2 1 2 1 2 VDDA V mA s s 1/fADC s 1/fADC pF LSB Unit
CSAMPLE Sample capacitor
*Note: ADC Accuracy vs. Negative Injection Current: For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB by 10K increase of the external analog source impedance. These measurements results and recommandations are done in the worst condition of injection: - negative injection - injection to an Input with analog capability ,adjacent to the enabled Analog Input - at 5V VDD supply, and worse temperature case.
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8-BIT ADC CHARACTERISTICS (Cont'd)
VDD RAIN VAIN Px.x/AINx Cpin 5pF VT = 0.6V leakage 1A SS VT = 0.6V
Sampling Switch
Cpin VT SS Chold
= input capacitance = threshold voltage = sampling switch
Chold 22.4 pF
= sample/hold capacitance leakage = leakage current at the pin due to various junctions
VSS
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8 PACKAGE CHARACTERISTICS
8.1 PACKAGE MECHANICAL DATA Figure 45. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width
Dim. A A1 B 0.10mm .004 seating plane C D E e H h K L N SO34S
mm Min 2.46 0.13 0.36 0.23 17.73 7.42 1.02 10.16 0.64 0.61 10.41 0.400 0.74 0.025 0 1.02 0.024 Typ Max Min 2.64 0.097 0.29 0.005 0.48 0.014 0.32 0.0091 18.06 0.698 7.59 0.292
inches Typ Max 0.104 0.0115 0.019 0.0125 0.711 0.299 0.040 0.410 0.029 8 0.040
Number of Pins 34
Figure 46. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width
E
Dim. mm Min 0.51 3.05 3.56 0.36 0.46 0.76 1.02 0.20 0.25 Typ Max Min 0.020 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 3.56 3.76 inches Typ Max 5.08 0.140 0.148 0.200
See Lead Detail
A A1
C
A2
b1
b e3 D
eA eB
b b1 C D E E1
27.43 27.94 28.45 1.080 1.100 1.120 9.91 10.41 11.05 0.390 0.410 0.435 7.62 8.89 1.78 10.16 12.70 2.54 3.05 Number of Pins 9.40 0.300 0.350 0.370 0.070 0.400 0.500 3.81 0.100 0.120 0.150 32
N E1 e 1 N/2
A2 A A1 L
e eA eB L N
VR01725J
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Figure 47. 32-Pin Shrink Ceramic Dual In-Line Package
Dim. A A1 B B1 C D D1 E E1 e G G1 G2 L O CDIP32SW N 9.45 0.38 0.36 0.64 0.20 mm Min Typ Max 3.63 0.015 0.46 0.58 0.014 0.018 0.023 0.89 1.14 0.025 0.035 0.045 0.25 0.36 0.008 0.010 0.014 26.67 10.16 1.78 9.40 14.73 1.12 3.30 7.37 32 1.050 0.400 0.070 0.370 0.580 0.044 0.130 0.290 Min inches Typ Max 0.143
29.41 29.97 30.53 1.158 1.180 1.202
9.91 10.36 0.372 0.390 0.408
Number of Pins
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9 DEVICE CONFIGURATION AND ORDERING INFORMATION
The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 9.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The customer code should be communicated to STMicroelectronics with the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Figure 48. Sales Type Coding Rules Family Version Code Sub family Subset Index Number of pins ROM Size Code Package Type Temperature Code ROM Code (three letters)
ST72 T 63 1 K 4 B 1 / xxx 0 = 25C B = Plastic DIP 4 = 16K K = 32/34 pins No letter = ROM 1 = Standard (0 to +70C) D = Ceramic DIP 2 = 8K E = EPROM M = Plastic SO 1 = 4K T = OTP Subset index : 1 = fully featured; other number = downgraded versions
Table 26. Ordering Information
Sales Type 1) ST72E631K4D0 ST72631K4M1/xxx ST72T631K4M1 ST72631K4B1/xxx ST72T631K4B1 ST72632K2M1/xxx ST72T632K2M1 ST72632K2B1/xxx ST72T632K2B1 ST72633K1M1/xxx ST72T633K1M1 ST72633K1B1/xxx ST72T633K1B1 Program Memory (bytes) 16K EPROM 16K ROM 16K OTP 16K ROM 16K OTP 8K ROM 8K OTP 8K ROM 8K OTP 4K ROM 4K OTP 4K ROM 4K OTP RAM Package (bytes) CSDIP32 512 SO34 PSDIP32 SO34 256 PSDIP32 SO34 256 PSDIP32
Note 1. /xxx stands for the ROM code name assigned by STMicroelectronics. Table 27. Development Tools
Development Tool Sales Type Real time emulator ST7263-EMU2 EPROM Programming Board ST72E63-EPB/EU ST72E63-EPB/US Remarks 220V Power Supply 110V Power Supply
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ST7263X MICROCONTROLLER OPTION LIST .... .... .... Contact: .... Phone No: . . . . Reference : . . . . Customer: Address: ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ..... ..... ..... ..... ..... .....
STMicroelectronics references: Device: [ ] ST72631K4 [ ] ST72632K2 [ ] ST72633K1 Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic Specify conditioning [ ] Standard (stick) [ ] Tape & Reel [ ] Die form Specify conditioning [ ] Inked unscribed wafers [ ] Inked and scribed wafers
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" For marking, one line is possible with maximum 13 characters. Authorized characters are letters, digits, '.', '-', '/' and spaces only.
We have checked the ROM code verification file returned to us by STMicroelectronics. It conforms exactly with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with device manufacture. Signature Date ............................ ............................
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ST7263
9.2 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION PROGRAMMING AND TOOLS AN985 EXECUTING CODE IN ST7 RAM AN986 USING THE ST7 INDIRECT ADDRESSING MODE AN987 ST7 IN-CIRCUIT PROGRAMMING AN988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN989 STARTING WITH ST7 HIWARE C AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 EXAMPLE DRIVERS AN969 ST7 SCI COMMUNICATION BETWEEN THE ST7 AND A PC AN970 ST7 SPI COMMUNICATION BETWEEN THE ST7 AND EPROM AN971 ST7 IC COMMUNICATION BETWEEN THE ST7 AND EPROM AN972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN974 REAL TIME CLOCK WITH THE ST7 TIMER OUTPUT COMPARE AN976 DRIVING A BUZZER USING THE ST7 PWM FUNCTION AN979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 USB MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 SOFTWARE IMPLEMENTATION OF IC BUS MASTER AN1046 ST7 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERAL AN1048 ST7 SOFTWARE LCD DRIVER AN1078 ST7 TIMER PWM DUTY CYCLE SWITCH FOR TRUE 0% or 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141 AN1130 BRUSHLESS DC MOTOR DRIVE WITH ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1182 USING THE ST7 USB LOW-SPEED FIRMWARE PRODUCT OPTIMIZATION AN982 USING CERAMIC RESONATORS WITH THE ST7 AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1070 ST7 CHECKSUM SELFCHECKING CAPABILITY AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP PRODUCT EVALUATION AN910 ST7 AND ST9 PERFORMANCE BENCHMARKING AN990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1086 ST7 / ST10U435 CAN-do SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F8
9.3 TO GET MORE INFORMATION To get the latest information on this product please use the ST web server: http://mcu.st.com/
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ST7263
10 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision 1.8 Main changes Changed status of the document (datasheet instead of preliminary data). Added Section 9.2 and section 9.3 on page 108. Date August 00
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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